VHDL Codes

Here are the some of the VHDL(HDL) codes
The list of the codes are
1. 3V ramp wave
2. 3V triangle wave
3. sine and triangle wave
4. square wave
5. trapezoidal wave
6. trapezoidal and triangle wave
7. sine and trapezoidal
8. 8:3 priority encoder
9. A kind of combination waveform
10. The scrolling ABCD in seven segment right/left

the above codes are have a time period of 1ms.(for waveforms)

VHDL CODES:

1. 3V RAMP WAVE
-- vhdl code for 3v ramp
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity ramp3v is
    Port ( clk : in  STD_LOGIC; --INTERNAL CLK OF 4 MHZ
           rst : in  STD_LOGIC;
           outp : out  STD_LOGIC_VECTOR (7 downto 0):="00000000");--DAC OUTPUT
end ramp3v;

architecture arch of ramp3v is
signal newclk:std_logic:='0';
begin
process(clk)

variable temp:integer:=0;
begin
if rising_edge(clk) then
temp:= temp+1;
if temp=8 then
newclk<=not newclk;
temp:=0;
end if;
end if;
end process;
process(newclk,rst)
variable reg:std_logic_vector(7 downto 0):="00000000";
begin
if rising_edge(newclk) then
case rst is
when '1'=> reg:="00000000";
when '0'=> reg:=reg+'1';
if reg = "10011010" then
reg:="00000000";
end if;
when others => null;
end case;
outp<=reg;
end if;
end process;
end arch;

2. 3V TRIANGLE WAVE
-- vhdl code for triangle wave with 3V
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity triangle3v is
    Port ( clk : in  STD_LOGIC;
           rst : in  STD_LOGIC;
           dac : out  STD_LOGIC_VECTOR (7 downto 0));
end triangle3v;

architecture arch of triangle3v is
signal newclk:std_logic:='0';
begin
process(clk)
variable temp:integer:=0;
begin
if rising_edge(clk) then
temp:=temp+1;
if temp=1 then
temp:=0;
newclk<=not newclk;
end if;
end if;
end process;
process(newclk,rst)
variable counter:std_logic_vector(7 downto 0):="00000000";
variable reg:std_logic_vector(7 downto 0):="10011001";
variable temp:integer:=0;
begin
if (rst='1' or temp=306) then
counter:="00000000";
temp:=0;
reg:="10011001";
elsif rising_edge(newclk) then
counter:=counter+'1';
temp:=temp+1;
if temp<=153 then
dac<= counter(7 downto 0);
elsif( temp > 153 and temp<=306) then
reg:=reg-1;
dac<=reg;
end if;
end if;
end process;
end arch;
3. SINE AND TRIANGLE WAVE
--sine and triangle
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity sine_triangle is
    Port ( clk : in  STD_LOGIC;
           dac : out  STD_LOGIC_VECTOR (7 downto 0));
end sine_triangle;

architecture arch of sine_triangle is
signal newclk:std_logic:='0';
signal i:integer range 0 to 90;
type sine is array(0 to 90) of integer range 0 to 255;
constant value:sine:=(0,9,18,27,36,44,53,62,70,79,87,96,
104,112,120,128,135,143,150,157,164,171,177,183,190,195,201,206,
211,216,221,225,229,233,236,240,243,245,247,249,251,253,254,254,
255,255,255,254,254,253,251,249,247,245,243,240,236,233,229,225,
221,216,211,206,201,195,190,183,177,171,164,157,150,143,135,128,
120,112,104,96,87,79,70,62,53,44,36,27,18,9,0);

begin
process(clk)
variable temp:integer:=0;
begin
if rising_edge(clk) then
temp:=temp+1;
if temp=8 then
newclk<=not newclk;
temp:=0;
end if;
end if;
end process;
process(newclk)
variable c:integer:=0;
variable counter:std_logic_vector(8 downto 0):="000000000";
variable reg:std_logic_vector(7 downto 0):="00000000";
begin
if rising_edge(newclk) then
if (c=0) then
dac<=conv_std_logic_vector(value(i),8);
i<=i+1;
if (i=90) then
i<=0;
c:=1;
end if;
else
counter:=counter+'1';
case counter(8) is
when '0' => reg:=counter(7 downto 0);
when '1' => reg:=not counter(7 downto 0);
when others =>COUNTER:=(OTHERS=>'0');
end case;
dac<=reg;
if(reg="00000000") then
c:=0;
end if;
end if;
end if;
end process;
end arch;

4. SQUARE WAVE

-- vhdl code for squre wave
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
entity squre is
    Port ( clk : in  STD_LOGIC;
           dac : out  STD_LOGIC_VECTOR (7 downto 0));
end squre;

architecture arch of squre is
signal newclk:std_logic:='0';
begin
process(clk)
variable temp:integer:=0;
begin
if rising_edge(clk) then
temp:=temp+1;
if temp=1000 then
newclk<= not newclk;
temp:=0;
end if;
end if;
end process;
process(newclk)
variable reg:std_logic_vector(7 downto 0):="00000000";
begin
if rising_edge(newclk) then
reg:=not reg;
end if;
dac<=reg;
end process;
end arch;

5.TRAPEZOIDAL WAVE
--vhdl code for trapeziodal wave with 1ms 1ms 1ms
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity TRAP is
port(clk:in std_logic;
DAC:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END TRAP;
ARCHITECTURE ARCH OF TRAP IS
SIGNAL TEMP:STD_LOGIC_VECTOR(3 DOWNTO 0):="0000";
BEGIN
PROCESS (CLK)
BEGIN
IF RISING_EDGE(CLK) THEN
TEMP<=TEMP+1;
END IF;
END PROCESS;
PROCESS(TEMP(3))
VARIABLE COUNT:STD_LOGIC_VECTOR(9 DOWNTO 0):="0000000000";
VARIABLE REG:STD_LOGIC_VECTOR(7 DOWNTO 0):="00000000";
BEGIN
IF RISING_EDGE(TEMP(3)) THEN
COUNT:=COUNT +1;
CASE COUNT(9 DOWNTO 8) IS
WHEN "00" =>REG:=COUNT (7 DOWNTO 0);
WHEN "01" =>REG:="11111111";
WHEN "10"=>REG:= NOT COUNT(7 DOWNTO 0);
WHEN OTHERS=>COUNT:=(OTHERS=>'0');
END CASE;
END IF;
DAC<=REG;
END PROCESS;
END ARCH;

6. TRAPEZOIDAL AND TRIANGLE WAVE
-- trapeziodal and triangle
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
entity trap_triangle is
    Port ( clk : in  STD_LOGIC;
           dac : out  STD_LOGIC_VECTOR (7 downto 0));
end trap_triangle;

architecture arch of trap_triangle is
signal newclk:std_logic:='0';
begin
process(clk)
variable temp:integer:=0;
begin
if rising_edge(clk) then
temp:=temp+1;
if temp=8 then
newclk<=not newclk;
temp:=0;
end if;
end if;
end process;
process(newclk)
variable counter:std_logic_vector(10 downto 0):="00000000000";
variable reg:std_logic_vector(7 downto 0):="00000000";
begin
if rising_edge(newclk) then
counter:=counter+1;
case counter(10 downto 8) is
when "000" => reg:=counter(7 downto 0);
when "001" => reg:= "11111111";
when "010" => reg:= not counter(7 downto 0);
when "011" => reg:= counter(7 downto 0);
when "100" => reg:= not counter(7 downto 0);
when others => counter:= (others =>'0');
end case;
dac<= reg;
end if;
end process;
end arch;

7.SINE AND TRAPEZOIDAL WAVE
-- sine wave and trapiziodal
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity sine_trepaziodal is
    Port ( clk : in  STD_LOGIC;
           dac : out  STD_LOGIC_VECTOR (7 downto 0));
end sine_trepaziodal;

architecture arch of sine_trepaziodal is
signal newclk:std_logic:='0';
signal i:integer range 0 to 90;
type sine is array( 0 to 90) of  integer range 0 to 255;
constant value:sine:=(0,9,18,27,36,44,53,62,70,79,87,96,
104,112,120,128,135,143,150,157,164,171,177,183,190,195,201,206,
211,216,221,225,229,233,236,240,243,245,247,249,251,253,254,254,
255,255,255,254,254,253,251,249,247,245,243,240,236,233,229,225,
221,216,211,206,201,195,190,183,177,171,164,157,150,143,135,128,
120,112,104,96,87,79,70,62,53,44,36,27,18,9,0);
begin
process(clk)
variable temp:integer:=0;
begin
if rising_edge(clk) then
temp:=temp+1;
if temp=8 then
newclk<=not newclk;
temp:=0;
end if;
end if;
end process;
process(newclk)
variable c:integer:=0;
variable counter:std_logic_vector(9 downto 0):="0000000000";
variable reg:std_logic_vector(7 downto 0):="00000000";
begin
if rising_edge(newclk) then
if (c=0) then
dac<= conv_std_logic_vector(value(i),8);
i<=i+1;
if (i=90) then
i<=0;
c:=1;
end if;
else
counter:=counter+1;
case counter(9 downto 8) is
when "00" => reg:=counter(7 downto 0);
when "01" => reg:="11111111";
when "10" => reg:= not counter(7 downto 0);
when others =>COUNTer:=(OTHERS=>'0');
end case;
dac<=reg;
if(reg="00000000") then
c:=0;
end if;
end if;
end if;
end process;

end arch;

8. PRIORITY ENCODER 8:3

--priority encoder

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity prior8to3 is

    Port ( x : in  STD_LOGIC_VECTOR (7 downto 0);

           y : out  STD_LOGIC_VECTOR (2 downto 0));

end prior8to3;

architecture arch of prior8to3 is

signal t:std_logic_vector(8 downto 0);

begin

y(2)<= x(7) or x(6) or x(4) or x(5);

t(0)<= not x(2);

t(1)<= not x(4);

t(2)<= not x(5);

t(3)<= not x(6);

t(4)<= t(3) and x(5);

t(5)<= t(3) and x(3) and t(1);

t(6)<= t(3) and x(1) and t(1) and t(0);

y(0)<=x(7) or t(4) or t(5) or t(6);

t(7)<= t(2) and t(1) and x(3);

t(8)<= t(2) and t(1) and x(2);

y(1)<= x(7) or x(6) or t(7) or t(8);

end arch;

9. combination waveform

--waveform
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
entity waveform is
    Port ( clk,rst : in  STD_LOGIC;
           dac : out  STD_LOGIC_VECTOR (7 downto 0));
end waveform;

architecture arch of waveform is

signal newclk:std_logic:='0';

begin
process(clk)
variable temp:integer:=0;
begin
if rising_edge(clk) then
temp:=temp+1;
if temp=8 then
newclk<=not newclk;
temp:=0;
end if;
end if;
end process;
process(newclk)
variable temp:integer:=0;
variable reg,counter:std_logic_vector(7 downto 0):="00000000";
begin
if (rst='1' or temp=765) then
reg:="00000000";
temp:=0;
elsif rising_edge(newclk) then
temp:=temp+1;
if(temp<=128) then
reg:=reg+'1';
elsif(temp>128 and temp<=255) then
reg:=reg;
elsif(temp>255 and temp<=382) then
reg:=reg+'1';
elsif(temp>382 and temp<=509) then
reg:=reg-'1';
elsif(temp>509 and temp<=637) then
reg:=reg;
else
reg:=reg-'1';
end if;

end if;
dac<=reg;
end process;
end arch;

The output for this code is will be as shown below

10. THE SCROLLING ABCD IN A SEVEN SEGMENT RIGHT/LEFT

--VHDL CODE FOR SCROLING LETTER
--- 0 for right shift 1 for left shift
--LIBRARY DECLARATION
Library Ieee;
Use ieee.std_logic_1164.all;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

--ENTITY DECLARATION
Entity vhdl_project is
Port(clk,s:in std_logic;
Disp: out std_logic_vector(3 downto 0);
Y:out std_logic_vector(6 downto 0));
End vhdl_project;
Architecture arch of vhdl_project is
Signal newclk,newclk1:std_logic :='0';--USED FOR DERIVED CLOCK
Begin
--CLOCK DIVIDER CODE
Process(clk)
Variable t1,t2:integer :=0;
Begin
If rising_edge(clk) then
T1:=t1+1;
T2:=t2+1;
If t1=4000000 then --CONVERTING INTERNAL CLK TO 1HZ CLK
T1:=0;
Newclk<=not  newclk;
End if;
If t2=2000 then
T2:=0;
Newclk1<=not  newclk1;
End if;
End if;
End process;
--SHIFTING AND DISPLAYING ABCD
Process(newclk,newclk1,s)
Variable c:integer:=0;
Variable t:std_logic_vector(1 downto 0) :="00";
Variable ssd1,ssd2,ssd3,ssd4:std_logic_vector(6 downto 0);
Begin
If rising_edge(newclk) then
If(s='0') then
T:=t+'1';
Else
T:=t-'1';
End if;
End if;
If rising_edge(newclk1) then
If (c=0) then
Disp<="1110";
Case t is
When "00" => ssd1:= "1111110";
When "01" => ssd1:= "1001110";
When "10" => ssd1:= "1111111";
When "11" => ssd1:= "1110111";
When others => null;
End Case;
C:=1;
Y<=ssd1;
Elsif(c=1) then
Disp<="1101";
Case t is
When "00" => ssd2:= "1001110";
When "01" => ssd2:= "1111111";
When "10" => ssd2:= "1110111";
When "11" => ssd2:= "1111110";
When others => null;
End Case;
C:=2;
Y<=ssd2;
Elsif (c=2) then
Disp<= "1011";
Case t is
When "00" => ssd3 := "1111111";
When "01" => ssd3 := "1110111";
When "10" => ssd3 := "1111110";
When "11" => ssd3 := "1001110";
When others => null;
End Case;
C:=3;
Y<= ssd3;
Elsif(C=3) THEN
Disp<="0111";
Case t is
When "00" => ssd4 :="1110111";
When "01" => ssd4 := "1111110";
When "10" => ssd4 := "1001110";
When "11" => ssd4 := "1111111";
When others=> null;
End Case;
C:=0;
Y<= ssd4;
End if;
End if;
End process;
End arch;

The ucf file for this code is
NET "CLK" LOC = "P52";
NET "S" LOC = "P74";
NET "Y<0>" LOC = "P18";
NET "Y<1>" LOC = "P17";
NET "Y<2>" LOC = "P15";
NET "Y<3>" LOC = "P14";
NET "Y<4>" LOC = "P13";
NET "Y<5>" LOC = "P12";
NET "Y<6>" LOC = "P1";
NET "DISP<3>" LOC = "P23";
NET "DISP<2>" LOC = "P24";
NET "DISP<1>" LOC = "P26";
NET "DISP<0>" LOC = "P27";