Dream Of Life

Prologue

Has anyone thought of life as a dream???
In this article I am going to share how my dream became my life…
In India there is a popular belief that early morning dreams come true..How true is this belief?? Is it a fact or a myth??? Well, that's up to you to decide..There is a difference between dreams and thoughts. Thought is that what the brain says and dream is that what the mind says..Now what is the difference between brain and mind?? That's a little bit of thinking for you..Thoughts can go wrong sometimes but coincidentally dreams do come true some or the other day..maybe without us even realizing it…With this small introduction I will now proceed to talking about the dream of my life..
Disclaimer: I enjoy playing with words, so read at your own risk..A high level of patience is recommended..😜
Dedicated to all my friends who appeared in my dreams…

!!!One day dream!!!
Introduction

Some of the most important events in my life are like as if it had happened before…It's like I have felt and experienced the same thing before and I can exactly predict what is going to happen in the next moment..It's like the event  happens in my mind first and then in a fraction of second it appears before me..It's like a strange memory that repeats itself in front of you..Well, words can't do justice to this feeling..Only those who have felt can relate to this…Do I call this coincidence or a super power?? Hmmmm can't decide..
I'll be now spreading light on those dreams of mine which have not yet come true..Now if that too comes true, then that calls for some serious thinking….It can't be sheer coincidence…

Childhood

Let's go 10 years back….This day is so memorable to me and I was so confused that its memories still linger on..I had a dream wherein my friends were playing around the pillars in the school and all of a sudden, they started fighting and it got so worse that it went on to beating each other….I did not remember the faces that had come in my dream and I had no clue as to why I got such a strange dream..Ignoring seemed the best option…
After some days( or months..not sure..long time you see), the same dream manifested itself before me in reality..Everything happened in a flash and I just couldn't do anything about it…
It felt so strange that I had dreamt about the same incident happening in the same place much before it actually occurred.
My thinking level was not so developed back then,  so I did not venture into giving too much work to my gray cells..
But one question still remained…Was this trying to tell me something..

College life

The golden phase of life...
The entry into college life brought along with it a lot of changes…A whole lot of new faces each holding within it  a unique personality..Friendly, confused, horrified..and the list goes on.. 
Here is one dream which is going to be true after some time, atleast hoping so…Well, there is nothing to lose in being a little optimistic..
Love adds spice to one's life and without love, life is boring...I guess you got where I am heading to…
Well, I too have a dream girl…a girl who appears in my dreams…but as luck would have it, I couldn’t see her face even once...I would describe her as someone with whom I can share everything...even the truth of my life…I have still not met anyone with whom I share the same feeling...Waiting for that day when I will be destined to meet her😉

Romantic dream!!

Every boy wishes to propose a girl in his own unique style…But in this case, I have a different perspective(a little hatke)…I believe that a girl will propose me and I will be the one deciding whether to accept it or not…
Once I was thinking about this before sleeping..That night my dream girl appeared and she was all ready to propose me…It started with a friend request…When I was speaking with my friends, she suddenly appeared and expressed her wish to speak personally with me…We went to a café and ordered some snacks and coffee..We were talking casually but she suddenly diverted the topic to a serious note and what I heard next, left me speechless..  Hope this dream also finds its way through into the reality of my life..

Thanks for reading this article....
A big thanks to all those who made way into my dreams because of which I could write this article.

Change Article

Hey....
I am posting one Article called Change!!!

Change change change!!!!!
This is a common term one can hear everywhere be it in politics, entertainment or science.
Charles Darwin, the father of evolution once quoted precisely “It is not the strongest of the species that survive, nor the most intelligent, but the one most responsive to change.”
Adaptability is the key for survival in this modern era of “technology”, where everyone strive for their existence.
What is change? Give it a serious thought.
It is perplexing to know that most of the changes have come about with wars, loss of lives, sacrifices and lots of bloodshed, where  the losses have mainly  occurred  for those who are unwilling to change and for those who are less adaptable to this  new dawn of irresolute world, I know you all are not yet convinced. Let me try my bit through an example, I guess most of you have heard of “THE MAHABARATH”, the longest epic found till date.
One can look at it with multiple states of mind. It serves as greatest proprietary of  the aspects like revenge, inhumanity, dharma  and what not!, but most interestingly it also has instances of  “CHANGE  AND ADAPLTABILITY” in it.
In Indian mythology it is believed that the god descends to the earth when there exists ultimate chaos, fear, lifelessness etc. Myth logically speaking the savior descends when the   dharma or deeds done by the people lose its existence and turns to adharma.
Now you might wonder how darma becomes  adarma??
To provide a scientific insight to this let me take an example of nuclear energy, a faithful provider of pain and gain.
It is used to generate electricity which is a most basic human necessity and it was also be used for mass destructions as in   Hiroshima and Nagasaki.... which  no one can forget.
But no one has ever thought of its complete abolishment WHY??
It is because; its boon overpowers its bane. Even Japan which was totally paralyzed by the nuclear effect once ,never thought of its elimination. There are many nuclear power plants which meets its daily electric consumption till date
Thus change eventual and natural. The change is within us. As the world demands one has to change lest, One’s existence shall be replaced by its extinction. Buckle up yourself and get ready for a change as the time for it has come
Now it’s upon us to let that change or to change the change...
But... from the ages it is evident that people always refuse the change...since most of them like routine robotic life where nothing seems actually interesting similar to an empty honeycoomb
Time will never wait for anyone nor does it have to. Be ready for a change or face the impacts of it, you always have a choice. The change has not even spared the creator of this universe “THE LORD KRISHNA”
He ended his journey in this earth which started the Kaliyug the black age...
Yes it indirectly says that the person who is unwilling for the change will perish.
Does Lord Krishna not have the strength to change the change that occurred??
Yes he had that strength but if he had used it then I would not be writing this nor would you have been reading this.
Presently this world is an epitome of anti-social work but believe me only a major change can set it right the roots of these points to us the so called most intelligent species we ever know!! -“The humans”
Are you convinced that a time for change has come at least now? Then just think of your contribution..
Try not to depend on others for a change. BE THE CHANGE if u succeed the does everyone follow and learn you. Enjoy your Life!!

Thank You!!!:-)

Occurrence of Letter(CASE SENSITIVE)

This is Microprocessor code for Displaying the Number of times that letter repeated the string is read from keyboard using BIOS function...
Algorithm is:

1. Initialize Data segment
2. read string from keyboard
3. point 2 pointer SI and DI to starting of string.
4. One is used for checking individual character of string with other (DI)
5. If any Character is repeated Increment BL
6. After Checking with all the character display the result...

The code is as follows...

;Finding The Occurance of Letter
;Author:AKSHATH KUMAR
;------------------------------------------
;---MACRO FOR DISPLAYING MSG---
printf macro msg
        lea dx,msg
        mov ah,09h
        int 21h
endm
;---------------------------------------------
data segment
msg1 db 10,13,"Enter the String:",10,13,"$"
str1 db 10h,?,10h dup(' ')
len dw 01h dup(0)
msg2 db 10,13,"$"
data ends
;--------------------
code segment
assume cs:code,ds:data
start:
        mov ax,data
        mov ds,ax
        printf msg1
        lea dx,str1
        mov ah,10
        int 21h
        printf msg2
        mov bx,0h
        mov cx,0h
        mov bl,str1[1]
        mov str1[bx+2],"$"
        lea di,str1+2
        mov cl,bl
        mov len,cx
again:
        mov al,ds:[di]
        push cx
        mov cx,len
        mov bl,0h
        lea si,str1+2
up:
   
        cmp al,ds:[si]
        jnz skip
        inc bl
skip:
        inc si
        loop up
        pop cx
        inc di
        add bl,30h
        mov dl,bl
        mov ah,02h
        int 21h
        loop again
        int 3h
code ends
end start

DOWNLOAD THE SOURCE CODE

Occurrence of Letter(CASE INSENSITIVE)

This is Microprocessor code for Displaying the Number of times that letter repeated the string is read from keyboard using BIOS function...
Algorithm is:

1. Initialize Data segment
2. read string from keyboard
3. point 2 pointer SI and DI to starting of string.
4. One is used for checking individual character of string with other (DI)
5. the concept used is case conversion logic
6. If any Character is repeated Increment BL
7. After Checking with all the character display the result...

The code is as follows...

;Finding The Occurrence of Letter(CASE INSENSITIVE)
;Author: AKSHATH KUMAR
;------------------------------------------
printf macro msg
        lea dx,msg
        mov ah,09h
        int 21h
endm
;---------------------------------------------
data segment
msg1 db 10,13,"Enter the String:",10,13,"$"
str1 db 10h,?,10h dup(' ')
len dw 01h dup(0)
msg2 db 10,13,"$"
data ends
;------------------
code segment
assume cs:code,ds:data
start:
        mov ax,data
        mov ds,ax
        printf msg1
        lea dx,str1
        mov ah,10
        int 21h
        printf msg2
        mov bx,0h
        mov cx,0h
        mov bl,str1[1]
        mov str1[bx+2],"$"
        lea di,str1+2
        mov cl,bl
        mov len,cx
        lea si,str1+2
change:
        mov al,[si]
        cmp al,5bh
        ja next
        add al,20h
next:
        mov [si],al
        inc si
        loop change

        mov cx,len
again:
        mov al,ds:[di]
        push cx
        mov cx,len
        mov bl,0h
        lea si,str1+2
up:
   
        cmp al,ds:[si]
        jnz skip
        inc bl
skip:
        inc si
        loop up
        pop cx
        inc di
        add bl,30h
        mov dl,bl
        mov ah,02h
        int 21h
        loop again
        int 3h
code ends
end start

DOWNLOAD SOURCE CODE

CASE CONVERSION

This is Microprocessor code for Converting Lower Case  letter to upper Case and Vice versa string is read from keyboard using BIOS function...
Algorithm is:

1. Initialize Data segment
2. read string from keyboard
3. point SI to start of string
4. Check Whether ASCII  value is less than 5Bh if yes add 20h
5. if ASCII value is greater than 60h then subtract 20h
6. Store the result in same location
7. repeat above steps for entire string length
8. After Checking with all the character display the result...

The code is:

;conversion of lower case to upper case

;Author: Akshath Kumar

;----------------------------------

data segment

msg1 db 10,13,"Enter string:",10,13,"$"

str1 db 10h,?,10h dup(' ')

len db 01h dup(0)

msg2 db 10,13,"Result is:",10,13,"$" 

data ends

;----------------------------------------

code segment

assume cs:code,ds:data

start:

        mov ax,data

        mov ds,ax

        mov bx,0h

        lea dx,msg1

        mov ah,09h

        int 21h

        lea dx,str1

        mov ah,10

        int 21h

        mov bl,str1[1]

        mov str1[bx+2],"$"

        mov len,bl

        mov bl,60h

        mov bh,20h

        lea si,str1+2

        mov cx,0h

        mov cl,len

up:     

        cmp [si],bl

        jae upper

        jb lower

upper:

        sub [si],bh

        jmp skip

lower:  add [si],bh

        jmp skip

skip:   inc si

        loop up

        lea dx,msg2

        mov ah,09h

        int 21h

        lea dx,str1+2

        mov ah,09h

        int 21h

        int 3h

        code ends

        end start

Download Source Code

VHDL Codes

Here are the some of the VHDL(HDL) codes
The list of the codes are
1. 3V ramp wave
2. 3V triangle wave
3. sine and triangle wave
4. square wave
5. trapezoidal wave
6. trapezoidal and triangle wave
7. sine and trapezoidal
8. 8:3 priority encoder
9. A kind of combination waveform
10. The scrolling ABCD in seven segment right/left

the above codes are have a time period of 1ms.(for waveforms)

VHDL CODES:

1. 3V RAMP WAVE
-- vhdl code for 3v ramp
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity ramp3v is
    Port ( clk : in  STD_LOGIC; --INTERNAL CLK OF 4 MHZ
           rst : in  STD_LOGIC;
           outp : out  STD_LOGIC_VECTOR (7 downto 0):="00000000");--DAC OUTPUT
end ramp3v;

architecture arch of ramp3v is
signal newclk:std_logic:='0';
begin
process(clk)

variable temp:integer:=0;
begin
if rising_edge(clk) then
temp:= temp+1;
if temp=8 then
newclk<=not newclk;
temp:=0;
end if;
end if;
end process;
process(newclk,rst)
variable reg:std_logic_vector(7 downto 0):="00000000";
begin
if rising_edge(newclk) then
case rst is
when '1'=> reg:="00000000";
when '0'=> reg:=reg+'1';
if reg = "10011010" then
reg:="00000000";
end if;
when others => null;
end case;
outp<=reg;
end if;
end process;
end arch;

2. 3V TRIANGLE WAVE
-- vhdl code for triangle wave with 3V
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity triangle3v is
    Port ( clk : in  STD_LOGIC;
           rst : in  STD_LOGIC;
           dac : out  STD_LOGIC_VECTOR (7 downto 0));
end triangle3v;

architecture arch of triangle3v is
signal newclk:std_logic:='0';
begin
process(clk)
variable temp:integer:=0;
begin
if rising_edge(clk) then
temp:=temp+1;
if temp=1 then
temp:=0;
newclk<=not newclk;
end if;
end if;
end process;
process(newclk,rst)
variable counter:std_logic_vector(7 downto 0):="00000000";
variable reg:std_logic_vector(7 downto 0):="10011001";
variable temp:integer:=0;
begin
if (rst='1' or temp=306) then
counter:="00000000";
temp:=0;
reg:="10011001";
elsif rising_edge(newclk) then
counter:=counter+'1';
temp:=temp+1;
if temp<=153 then
dac<= counter(7 downto 0);
elsif( temp > 153 and temp<=306) then
reg:=reg-1;
dac<=reg;
end if;
end if;
end process;
end arch;
3. SINE AND TRIANGLE WAVE
--sine and triangle
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity sine_triangle is
    Port ( clk : in  STD_LOGIC;
           dac : out  STD_LOGIC_VECTOR (7 downto 0));
end sine_triangle;

architecture arch of sine_triangle is
signal newclk:std_logic:='0';
signal i:integer range 0 to 90;
type sine is array(0 to 90) of integer range 0 to 255;
constant value:sine:=(0,9,18,27,36,44,53,62,70,79,87,96,
104,112,120,128,135,143,150,157,164,171,177,183,190,195,201,206,
211,216,221,225,229,233,236,240,243,245,247,249,251,253,254,254,
255,255,255,254,254,253,251,249,247,245,243,240,236,233,229,225,
221,216,211,206,201,195,190,183,177,171,164,157,150,143,135,128,
120,112,104,96,87,79,70,62,53,44,36,27,18,9,0);

begin
process(clk)
variable temp:integer:=0;
begin
if rising_edge(clk) then
temp:=temp+1;
if temp=8 then
newclk<=not newclk;
temp:=0;
end if;
end if;
end process;
process(newclk)
variable c:integer:=0;
variable counter:std_logic_vector(8 downto 0):="000000000";
variable reg:std_logic_vector(7 downto 0):="00000000";
begin
if rising_edge(newclk) then
if (c=0) then
dac<=conv_std_logic_vector(value(i),8);
i<=i+1;
if (i=90) then
i<=0;
c:=1;
end if;
else
counter:=counter+'1';
case counter(8) is
when '0' => reg:=counter(7 downto 0);
when '1' => reg:=not counter(7 downto 0);
when others =>COUNTER:=(OTHERS=>'0');
end case;
dac<=reg;
if(reg="00000000") then
c:=0;
end if;
end if;
end if;
end process;
end arch;

4. SQUARE WAVE

-- vhdl code for squre wave
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
entity squre is
    Port ( clk : in  STD_LOGIC;
           dac : out  STD_LOGIC_VECTOR (7 downto 0));
end squre;

architecture arch of squre is
signal newclk:std_logic:='0';
begin
process(clk)
variable temp:integer:=0;
begin
if rising_edge(clk) then
temp:=temp+1;
if temp=1000 then
newclk<= not newclk;
temp:=0;
end if;
end if;
end process;
process(newclk)
variable reg:std_logic_vector(7 downto 0):="00000000";
begin
if rising_edge(newclk) then
reg:=not reg;
end if;
dac<=reg;
end process;
end arch;

5.TRAPEZOIDAL WAVE
--vhdl code for trapeziodal wave with 1ms 1ms 1ms
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity TRAP is
port(clk:in std_logic;
DAC:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END TRAP;
ARCHITECTURE ARCH OF TRAP IS
SIGNAL TEMP:STD_LOGIC_VECTOR(3 DOWNTO 0):="0000";
BEGIN
PROCESS (CLK)
BEGIN
IF RISING_EDGE(CLK) THEN
TEMP<=TEMP+1;
END IF;
END PROCESS;
PROCESS(TEMP(3))
VARIABLE COUNT:STD_LOGIC_VECTOR(9 DOWNTO 0):="0000000000";
VARIABLE REG:STD_LOGIC_VECTOR(7 DOWNTO 0):="00000000";
BEGIN
IF RISING_EDGE(TEMP(3)) THEN
COUNT:=COUNT +1;
CASE COUNT(9 DOWNTO 8) IS
WHEN "00" =>REG:=COUNT (7 DOWNTO 0);
WHEN "01" =>REG:="11111111";
WHEN "10"=>REG:= NOT COUNT(7 DOWNTO 0);
WHEN OTHERS=>COUNT:=(OTHERS=>'0');
END CASE;
END IF;
DAC<=REG;
END PROCESS;
END ARCH;

6. TRAPEZOIDAL AND TRIANGLE WAVE
-- trapeziodal and triangle
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
entity trap_triangle is
    Port ( clk : in  STD_LOGIC;
           dac : out  STD_LOGIC_VECTOR (7 downto 0));
end trap_triangle;

architecture arch of trap_triangle is
signal newclk:std_logic:='0';
begin
process(clk)
variable temp:integer:=0;
begin
if rising_edge(clk) then
temp:=temp+1;
if temp=8 then
newclk<=not newclk;
temp:=0;
end if;
end if;
end process;
process(newclk)
variable counter:std_logic_vector(10 downto 0):="00000000000";
variable reg:std_logic_vector(7 downto 0):="00000000";
begin
if rising_edge(newclk) then
counter:=counter+1;
case counter(10 downto 8) is
when "000" => reg:=counter(7 downto 0);
when "001" => reg:= "11111111";
when "010" => reg:= not counter(7 downto 0);
when "011" => reg:= counter(7 downto 0);
when "100" => reg:= not counter(7 downto 0);
when others => counter:= (others =>'0');
end case;
dac<= reg;
end if;
end process;
end arch;

7.SINE AND TRAPEZOIDAL WAVE
-- sine wave and trapiziodal
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity sine_trepaziodal is
    Port ( clk : in  STD_LOGIC;
           dac : out  STD_LOGIC_VECTOR (7 downto 0));
end sine_trepaziodal;

architecture arch of sine_trepaziodal is
signal newclk:std_logic:='0';
signal i:integer range 0 to 90;
type sine is array( 0 to 90) of  integer range 0 to 255;
constant value:sine:=(0,9,18,27,36,44,53,62,70,79,87,96,
104,112,120,128,135,143,150,157,164,171,177,183,190,195,201,206,
211,216,221,225,229,233,236,240,243,245,247,249,251,253,254,254,
255,255,255,254,254,253,251,249,247,245,243,240,236,233,229,225,
221,216,211,206,201,195,190,183,177,171,164,157,150,143,135,128,
120,112,104,96,87,79,70,62,53,44,36,27,18,9,0);
begin
process(clk)
variable temp:integer:=0;
begin
if rising_edge(clk) then
temp:=temp+1;
if temp=8 then
newclk<=not newclk;
temp:=0;
end if;
end if;
end process;
process(newclk)
variable c:integer:=0;
variable counter:std_logic_vector(9 downto 0):="0000000000";
variable reg:std_logic_vector(7 downto 0):="00000000";
begin
if rising_edge(newclk) then
if (c=0) then
dac<= conv_std_logic_vector(value(i),8);
i<=i+1;
if (i=90) then
i<=0;
c:=1;
end if;
else
counter:=counter+1;
case counter(9 downto 8) is
when "00" => reg:=counter(7 downto 0);
when "01" => reg:="11111111";
when "10" => reg:= not counter(7 downto 0);
when others =>COUNTer:=(OTHERS=>'0');
end case;
dac<=reg;
if(reg="00000000") then
c:=0;
end if;
end if;
end if;
end process;

end arch;

8. PRIORITY ENCODER 8:3

--priority encoder

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity prior8to3 is

    Port ( x : in  STD_LOGIC_VECTOR (7 downto 0);

           y : out  STD_LOGIC_VECTOR (2 downto 0));

end prior8to3;

architecture arch of prior8to3 is

signal t:std_logic_vector(8 downto 0);

begin

y(2)<= x(7) or x(6) or x(4) or x(5);

t(0)<= not x(2);

t(1)<= not x(4);

t(2)<= not x(5);

t(3)<= not x(6);

t(4)<= t(3) and x(5);

t(5)<= t(3) and x(3) and t(1);

t(6)<= t(3) and x(1) and t(1) and t(0);

y(0)<=x(7) or t(4) or t(5) or t(6);

t(7)<= t(2) and t(1) and x(3);

t(8)<= t(2) and t(1) and x(2);

y(1)<= x(7) or x(6) or t(7) or t(8);

end arch;

9. combination waveform

--waveform
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
entity waveform is
    Port ( clk,rst : in  STD_LOGIC;
           dac : out  STD_LOGIC_VECTOR (7 downto 0));
end waveform;

architecture arch of waveform is

signal newclk:std_logic:='0';

begin
process(clk)
variable temp:integer:=0;
begin
if rising_edge(clk) then
temp:=temp+1;
if temp=8 then
newclk<=not newclk;
temp:=0;
end if;
end if;
end process;
process(newclk)
variable temp:integer:=0;
variable reg,counter:std_logic_vector(7 downto 0):="00000000";
begin
if (rst='1' or temp=765) then
reg:="00000000";
temp:=0;
elsif rising_edge(newclk) then
temp:=temp+1;
if(temp<=128) then
reg:=reg+'1';
elsif(temp>128 and temp<=255) then
reg:=reg;
elsif(temp>255 and temp<=382) then
reg:=reg+'1';
elsif(temp>382 and temp<=509) then
reg:=reg-'1';
elsif(temp>509 and temp<=637) then
reg:=reg;
else
reg:=reg-'1';
end if;

end if;
dac<=reg;
end process;
end arch;

The output for this code is will be as shown below

10. THE SCROLLING ABCD IN A SEVEN SEGMENT RIGHT/LEFT

--VHDL CODE FOR SCROLING LETTER
--- 0 for right shift 1 for left shift
--LIBRARY DECLARATION
Library Ieee;
Use ieee.std_logic_1164.all;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

--ENTITY DECLARATION
Entity vhdl_project is
Port(clk,s:in std_logic;
Disp: out std_logic_vector(3 downto 0);
Y:out std_logic_vector(6 downto 0));
End vhdl_project;
Architecture arch of vhdl_project is
Signal newclk,newclk1:std_logic :='0';--USED FOR DERIVED CLOCK
Begin
--CLOCK DIVIDER CODE
Process(clk)
Variable t1,t2:integer :=0;
Begin
If rising_edge(clk) then
T1:=t1+1;
T2:=t2+1;
If t1=4000000 then --CONVERTING INTERNAL CLK TO 1HZ CLK
T1:=0;
Newclk<=not  newclk;
End if;
If t2=2000 then
T2:=0;
Newclk1<=not  newclk1;
End if;
End if;
End process;
--SHIFTING AND DISPLAYING ABCD
Process(newclk,newclk1,s)
Variable c:integer:=0;
Variable t:std_logic_vector(1 downto 0) :="00";
Variable ssd1,ssd2,ssd3,ssd4:std_logic_vector(6 downto 0);
Begin
If rising_edge(newclk) then
If(s='0') then
T:=t+'1';
Else
T:=t-'1';
End if;
End if;
If rising_edge(newclk1) then
If (c=0) then
Disp<="1110";
Case t is
When "00" => ssd1:= "1111110";
When "01" => ssd1:= "1001110";
When "10" => ssd1:= "1111111";
When "11" => ssd1:= "1110111";
When others => null;
End Case;
C:=1;
Y<=ssd1;
Elsif(c=1) then
Disp<="1101";
Case t is
When "00" => ssd2:= "1001110";
When "01" => ssd2:= "1111111";
When "10" => ssd2:= "1110111";
When "11" => ssd2:= "1111110";
When others => null;
End Case;
C:=2;
Y<=ssd2;
Elsif (c=2) then
Disp<= "1011";
Case t is
When "00" => ssd3 := "1111111";
When "01" => ssd3 := "1110111";
When "10" => ssd3 := "1111110";
When "11" => ssd3 := "1001110";
When others => null;
End Case;
C:=3;
Y<= ssd3;
Elsif(C=3) THEN
Disp<="0111";
Case t is
When "00" => ssd4 :="1110111";
When "01" => ssd4 := "1111110";
When "10" => ssd4 := "1001110";
When "11" => ssd4 := "1111111";
When others=> null;
End Case;
C:=0;
Y<= ssd4;
End if;
End if;
End process;
End arch;

The ucf file for this code is
NET "CLK" LOC = "P52";
NET "S" LOC = "P74";
NET "Y<0>" LOC = "P18";
NET "Y<1>" LOC = "P17";
NET "Y<2>" LOC = "P15";
NET "Y<3>" LOC = "P14";
NET "Y<4>" LOC = "P13";
NET "Y<5>" LOC = "P12";
NET "Y<6>" LOC = "P1";
NET "DISP<3>" LOC = "P23";
NET "DISP<2>" LOC = "P24";
NET "DISP<1>" LOC = "P26";
NET "DISP<0>" LOC = "P27";

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